1. Field of the Invention
The present invention relates to a video signal processing device including an analog/digital converter for converting an analog video signal into a digital video signal and a clock signal generating circuit for supplying clock signals to the analog/digital converter.
2. Description of the Related Art
Audio devices, navigation devices, and the like mount therein video signal processing devices that convert analog video signals input from a plurality of kinds of devices such as radio wave receiving devices and DVD players into digital video signals, and cause the digital video signals to be displayed on the display portions of liquid crystal displays and the like.
Video signal processing devices mount therein PLL (Phase-Locked Loop) circuits and DLL (Delay-Locked Loop) circuits such that clock signals generated in the PLL circuits or the DLL circuits are used as sampling clocks for converting analog video signals input to the devices into digital video signals.
The PLL circuit includes a voltage control oscillator (VCO) that carries out feedback by generating a clock signal of a predetermined frequency on the basis of a phase difference and a frequency difference between a feedback signal and a frequency-controlled horizontal synchronous signal separated from the input analog video signal, and generates a clock signal synchronized with the horizontal synchronous signal.
The DLL circuit is provided with a reference oscillator and a plurality of delay circuits instead of the voltage control oscillator (VCO) and generates a clock signal with its edges aligned with those of a composite synchronous signal separated from the input analog video signal.
When the input analog video signal is a standard signal, which satisfies a television signal standard such as the NTSC system, or when the input analog video signal is a signal capable of being phase locked by the PLL circuit on the basis of a horizontal synchronous signal separated from the input analog video signal, then the clock signal generated at the PLL circuit is used as a sampling clock.
This is because sampling the input analog video signal on the basis of the clock signal generated at the PLL circuit results in a more beautiful video display with reduced jitters than sampling on the basis of the clock signal generated at the DLL circuit.
However, when the input analog video signal is a non-standard signal, which deviates from a television signal standard, or when the input analog video signal is a signal incapable of being phase locked by the PLL circuit on the basis of a horizontal synchronous signal separated from the input analog video signal, then the clock signal generated at the DLL circuit is used as a sampling clock.
In view of this, in the conventional video signal processing devices, either the PLL circuit or the DLL circuit was selected uniformly depending on the kind of the signal generating source of the input analog video signal, and the selected clock signal was supplied as the sampling clock signal to the analog/digital converter.
For example, when the signal generating source of the input analog video signal input to the video signal processing device was a radio wave receiving device or a DVD player, the clock signal generated at the PLL circuit was selected as the sampling clock, while when the signal generating source was a VHS video cassette recorder, the clock signal generated at the DLL circuit was selected as the sampling clock.
This is because although the radio wave receiving device and the DVD player output a standard signal satisfying the television signal standard, the VHS video cassette recorder highly possibly outputs a non-standard signal deviating from the television signal standard if the recorder carries out a playback operation with an expanded or contracted video tape, since video tapes used for playback operations of the recorder may be expanded or contracted due to repeated use, temperature properties, and the like. This may disable the phase locking by the PLL circuit.
Japanese Unexamined Patent Publication No. 2006-115113 discloses a clock generation apparatus capable of shifting only the phase of the sampled video signal when a synchronous signal and a video signal are input separately.
Specifically, the clock generation apparatus includes: a first ADC for inputting and digitizing a synchronous signal or a video signal on which a synchronous signal is superimposed and outputting the digitized signal; a second ADC for inputting and digitizing a video signal and outputting the digitized signal; a PLL circuit for generating a clock on the basis of a horizontal synchronous signal separated from the output signal from the first ADC and supplying the clock to the first ADC; a DLL circuit for delaying the clock output from the PLL circuit to output multiple-phase clocks; and a clock selection circuit for selecting one of the input multiple-phase clocks and supplying the selected clock to the second ADC.
However, the video signal processing devices adapted to make a proper use of the PLL circuit and the DLL circuit in generating sampling clocks depending on the kind of the signal generating source of the input analog video signal may pose the following problems.
First, for the video signal processing device to switch between the PLL circuit and the DLL circuit to supply a clock signal to the analog/digital converter, the kind of the signal generating source of the input analog video signal must be identified, thereby necessitating a dedicated circuit.
Next, although using the clock signal of the PLL circuit generally results in a more beautiful video display with reduced jitters, the video cassette recorder uniformly uses the clock signal of the DLL circuit, resulting in video degradation in quality.
There are cases where the phase locking by the PLL circuit is possible depending on the state of the recording medium, such as video tape, used in the playback operation of the video cassette recorder. In such cases, selecting the clock signal of the PLL circuit results in a more beautiful video display.
Contrarily, even in the case of a signal generating source of a standard signal where the clock signal of the PLL circuit is selected, the phase locking by the PLL circuit may be disabled by the influence of the environment and the like, resulting in a video distortion.
In this case, there is a case where selecting the clock signal of the DLL circuit results in a normal video display.